TY - JOUR
T1 - The address translation unit of the data-intensive architecture (DIVA) system
AU - Chiueh, Her-Ming
AU - Draper, Jeffrey
AU - Mediratta, Sumit
AU - Sondeen, Jeff
PY - 2002/9/24
Y1 - 2002/9/24
N2 - The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.
AB - The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.
UR - http://www.scopus.com/inward/record.url?scp=84893720979&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:84893720979
SN - 1930-8833
SP - 767
EP - 770
JO - European Solid-State Circuits Conference
JF - European Solid-State Circuits Conference
M1 - 1471640
T2 - 28th European Solid-State Circuits Conference, ESSCIRC 2002
Y2 - 24 September 2002 through 26 September 2002
ER -