The address translation unit of the data-intensive architecture (DIVA) system

Her-Ming Chiueh, Jeffrey Draper, Sumit Mediratta, Jeff Sondeen

研究成果: Conference article同行評審

3 引文 斯高帕斯(Scopus)

摘要

The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.

原文English
文章編號1471640
頁(從 - 到)767-770
頁數4
期刊European Solid-State Circuits Conference
出版狀態Published - 24 9月 2002
事件28th European Solid-State Circuits Conference, ESSCIRC 2002 - Florence, Italy
持續時間: 24 9月 200226 9月 2002

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