Testing strategies for a 9T sub-threshold SRAM

Hao Yu Yang*, Chen Wei Lin, Hung Hsin Chen, Chia-Tso Chao, Ming Hsien Tu, Shyh-Jye Jou, Ching Te Chuang


    研究成果: Conference contribution同行評審

    1 引文 斯高帕斯(Scopus)


    Due to the increasing demands of lower-power devices, a lot of research effort has been devoted to develop new SRAM cell designs that can be effectively and economically operated at the subthreshold region. However, each new SRAM cell design has its own cell structure and design techniques, which may result in different faulty behaviors than the conventional 6T SRAMs and require specialized test methods to detect those uncovered fault models. In this paper, we focus on developing the test methods for testing a new 9T subthreshold SRAM design, which utilizes single bit-line read/write, two write word-lines for writing different values, and a separate read path. A mixed march algorithm with different background and address-traverse directions is proposed to detect various uncovered fault models and validated through real test chips. A new specialized technique of floating bit-line attacking is also presented to detect the stability faults, which cannot be effectively detected by applying the conventional test methods, for the new 9T SRAM design.

    主出版物標題ITC 2012 - International Test Conference 2012, Proceedings
    出版狀態Published - 1 12月 2012
    事件2012 International Test Conference, ITC 2012 - Anaheim, CA, United States
    持續時間: 6 11月 20128 11月 2012


    名字Proceedings - International Test Conference


    Conference2012 International Test Conference, ITC 2012
    國家/地區United States
    城市Anaheim, CA


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