@inproceedings{d7ba376fc4cc425aad53892074bb9cbb,
title = "Testing retention flip-flops in power-gated designs",
abstract = "This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.",
author = "Hsu, {Hao Wen} and Kuo, {Shih Hua} and Chang, {Wen Hsiang} and Chen, {Shi Hao} and Chang, {Ming Tung} and Chia-Tso Chao",
year = "2013",
month = aug,
day = "14",
doi = "10.1109/VTS.2013.6548880",
language = "English",
isbn = "9781467355438",
series = "Proceedings of the IEEE VLSI Test Symposium",
booktitle = "Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013",
note = "2013 IEEE 31st VLSI Test Symposium, VTS 2013 ; Conference date: 29-04-2013 Through 01-05-2013",
}