Testing methodology of embedded DRAMs

Hao Yu Yang*, Chi Min Chang, Chia-Tso Chao, Rei Fu Huang, Shih Chin Lin

*此作品的通信作者

    研究成果: Article同行評審

    17 引文 斯高帕斯(Scopus)

    摘要

    The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

    原文English
    文章編號5981413
    頁(從 - 到)1715-1728
    頁數14
    期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
    20
    發行號9
    DOIs
    出版狀態Published - 1 1月 2012

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