Testing Methodology of Embedded DRAMs

Chi Min Chang*, Chia-Tso Chao, Rei Fu Huangt, Ding Yuan Chen

*此作品的通信作者

    研究成果: Conference contribution同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    The embedded-DRAMtesting mixes up the techniques used for DRAM testing and SRAM testing since an embedded- DRAM core combines DRAM cells with an SRAM interface (the so-called 1 T-SRAM architecture). In this paper, we first present our test algorithm for embedded-DRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the embedded-DRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Theexperimental results are collected based on 1-lot wafers with an 16Mb embedded DRAM core.

    原文English
    主出版物標題Proceedings - International Test Conference 2008, ITC 2008
    DOIs
    出版狀態Published - 2008
    事件International Test Conference 2008, ITC 2008 - Santa Clara, CA, United States
    持續時間: 28 10月 200830 10月 2008

    出版系列

    名字Proceedings - International Test Conference
    ISSN(列印)1089-3539

    Conference

    ConferenceInternational Test Conference 2008, ITC 2008
    國家/地區United States
    城市Santa Clara, CA
    期間28/10/0830/10/08

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