Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Ming-Dou Ker*, Jeng Jie Peng, Hsin Chin Jiang

*此作品的通信作者

    研究成果: Paper › 同行評審

    1 引文 斯高帕斯（Scopus）

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    Engineering & Materials Science