Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Ming-Dou Ker*, Jeng Jie Peng, Hsin Chin Jiang

*此作品的通信作者

    研究成果: Paper同行評審

    1 引文 斯高帕斯(Scopus)

    指紋

    深入研究「Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's」主題。共同形成了獨特的指紋。

    Engineering & Materials Science