Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Ming-Dou Ker; Jeng Jie Peng; Hsin Chin Jiang

doi:10.1109/ICMTS.2003.1197455

Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Ming-Dou Ker^*, Jeng Jie Peng, Hsin Chin Jiang

^*此作品的通信作者

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

摘要

For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.

原文	English
頁面	161-166
頁數	6
DOIs	https://doi.org/10.1109/ICMTS.2003.1197455
出版狀態	Published - 3月 2003
事件	IEEE International Conference on Microelectronic Test Structures - Monterey, CA, 美國持續時間: 17 3月 2003 → 20 3月 2003

Conference

Conference	IEEE International Conference on Microelectronic Test Structures
國家/地區	美國
城市	Monterey, CA
期間	17/03/03 → 20/03/03

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10.1109/ICMTS.2003.1197455

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Link to publication in Scopus

引用此

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title = "Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's",

abstract = "For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.",

author = "Ming-Dou Ker and Peng, {Jeng Jie} and Jiang, {Hsin Chin}",

year = "2003",

month = mar,

doi = "10.1109/ICMTS.2003.1197455",

language = "English",

pages = "161--166",

note = "IEEE International Conference on Microelectronic Test Structures ; Conference date: 17-03-2003 Through 20-03-2003",

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TY - CONF

T1 - Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

AU - Ker, Ming-Dou

AU - Peng, Jeng Jie

AU - Jiang, Hsin Chin

PY - 2003/3

Y1 - 2003/3

N2 - For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.

AB - For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-μm 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.

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U2 - 10.1109/ICMTS.2003.1197455

DO - 10.1109/ICMTS.2003.1197455

M3 - Paper

AN - SCOPUS:0037628043

SP - 161

EP - 166

T2 - IEEE International Conference on Microelectronic Test Structures

Y2 - 17 March 2003 through 20 March 2003

ER -

Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

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Conference

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