Test Generation for Defect-Based Faults of Scan Flip-Flops

Yu Teng Nien, Chen Hong Li, Pei Yin Wu, Yung Jheng Wang, Kai Chiang Wu, Mango C.T. Chao

研究成果: Conference contribution同行評審


When testing scan flip-flops (SFFs), chain test is first applied to ensure the functionality of scan chains and to detect the majority of stuck-at (SA) and transition delay (TD) faults along scan paths. However, there still exist some defects inside scan cells that cannot be effectively detected by chain test or conventional SA and TD patterns. This paper presents five cell-aware (CA) fault models to explicitly target the defects inside scan flip-flops. The proposed static shift (SS) and dynamic shift (DS) faults identify the defects detectable by chain test. For the defects escaping chain test, static single-capture (SSC) faults target the defects detectable when SFFs are in one-cycle capture mode, while static double-capture (SDC) and dynamic double-capture (DDC) faults target those detectable when SFFs are in two-cycle capture mode. The identified CA faults of SFFs are output in a format compatible with a commercial ATPG tool for pattern generation. Experimental results on large IWLS05 benchmarks demonstrate that our proposed faults cannot be fully covered by conventional SA and TD patterns and hence require dedicated test patterns to detect.

主出版物標題Proceedings - 2023 IEEE 41st VLSI Test Symposium, VTS 2023
發行者IEEE Computer Society
出版狀態Published - 2023
事件41st IEEE VLSI Test Symposium, VTS 2023 - San Diego, United States
持續時間: 24 4月 202326 4月 2023


名字Proceedings of the IEEE VLSI Test Symposium


Conference41st IEEE VLSI Test Symposium, VTS 2023
國家/地區United States
城市San Diego


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