Temporal multithreading architecture design for a Java processor

Hung Cheng Su, Tsung Han Wu, Chun-Jen Tsai

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

In this paper, we presents the design of a hardware temporal multi-threading architecture for a Java processor. The Java virtual machine (JVM) model is a stack machine where the process state is the snapshot of the Java stack. If the runtime stack is stored (or cached) in on-chip memory for performance reasons, the backup and restoration of the Java runtime stacks for context switching would be expensive operations. We propose a Ping-Pong buffer architecture in this paper to facilitate fully hardware-based multi-threading capability for a Java processor. The proposed hardware architecture has been implemented and verified on an FPGA platform, Xilinx ML605. The experimental results show that the proposed context-switching efficiency is much higher than that of a software-based VM such as the CVM-JIT. Therefore, the proposed hardwired Java processor is promising for embedded applications that require heavy multi-threading operations.

原文English
主出版物標題2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面2201-2204
頁數4
ISBN(列印)9781479934324
DOIs
出版狀態Published - 2014
事件2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
持續時間: 1 6月 20145 6月 2014

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
國家/地區Australia
城市Melbourne, VIC
期間1/06/145/06/14

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