TY - JOUR

T1 - Temperature-aware floorplanning via geometric programming

AU - Chen, Ying Chieh

AU - Li, Yiming

PY - 2010/4

Y1 - 2010/4

N2 - With microprocessor power densities escalating rapidly when technology scales below nanometer regime, there is an exigent need for developing innovative cooling systems for electronic product design. The high temperature of chips greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling systems significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) for the optimization problem of temperature reduction and chip area floorplanning. We notice that the formulated model is a nonlinear convex problem; consequently, its solution can be solved GP method. Based upon an incremental floorplanning problem together with the GP model, the temperature-aware floorplanning scheme significantly reduces peak module temperature with minimal chip area impact. For Microelectronics Center of North Carolina (MCNC) ami33 under a testing environment temperature of 0 {ring operator}C, compared with the maximum temperature of the original module, the maximum temperature of the optimized one could be reduced from 90 {ring operator}C to 10 {ring operator}C, where the minimized chip area is about 700 mm2. For the case of MCNC ami49, the maximum temperature reduction is 60 {ring operator}C (i.e., its reduction is from 65 {ring operator}C to 5 {ring operator}C) with a minimal chip area of 2500 mm2. We have numerically found a floorplan which can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance simultaneously.

AB - With microprocessor power densities escalating rapidly when technology scales below nanometer regime, there is an exigent need for developing innovative cooling systems for electronic product design. The high temperature of chips greatly affects its reliability, raises the leakage power consumed to unprecedented levels, and makes cooling systems significantly more expensive. The maximum temperature of a block in a chip depends not only on its own power density, but also on the chip area in each blocks. In this paper, we employ geometric programming (GP) for the optimization problem of temperature reduction and chip area floorplanning. We notice that the formulated model is a nonlinear convex problem; consequently, its solution can be solved GP method. Based upon an incremental floorplanning problem together with the GP model, the temperature-aware floorplanning scheme significantly reduces peak module temperature with minimal chip area impact. For Microelectronics Center of North Carolina (MCNC) ami33 under a testing environment temperature of 0 {ring operator}C, compared with the maximum temperature of the original module, the maximum temperature of the optimized one could be reduced from 90 {ring operator}C to 10 {ring operator}C, where the minimized chip area is about 700 mm2. For the case of MCNC ami49, the maximum temperature reduction is 60 {ring operator}C (i.e., its reduction is from 65 {ring operator}C to 5 {ring operator}C) with a minimal chip area of 2500 mm2. We have numerically found a floorplan which can reduce the maximum temperature of the chip and minimize the chip area while maintaining comparable performance simultaneously.

KW - Floorplanning

KW - Geometric programming

KW - Incremental floorplanning

KW - Nonlinear programming

KW - Numerical optimization

KW - Optimal designs

KW - Programming involving graphs or networks

KW - Temperature aware

KW - VLSI circuit physical design

UR - http://www.scopus.com/inward/record.url?scp=76449094178&partnerID=8YFLogxK

U2 - 10.1016/j.mcm.2009.08.026

DO - 10.1016/j.mcm.2009.08.026

M3 - Article

AN - SCOPUS:76449094178

SN - 0895-7177

VL - 51

SP - 927

EP - 934

JO - Mathematical and Computer Modelling

JF - Mathematical and Computer Modelling

IS - 7-8

ER -