Technology, performance, and computer-aided design of three-dimensional integrated circuits

Shamik Das*, Chuan Seng Tan, Andy Fan, Nisha Checka, Kuan-Neng Chen, Rafael Reif

*此作品的通信作者

    研究成果同行評審

    102 引文 斯高帕斯(Scopus)

    摘要

    We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3-D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3-D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3-D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.

    原文English
    頁面108-115
    頁數8
    DOIs
    出版狀態Published - 4月 2004
    事件Proceedings of the International Symposium on Physical Design, ISPD 2004 - Phoenix, AZ, 美國
    持續時間: 18 4月 200421 4月 2004

    Conference

    ConferenceProceedings of the International Symposium on Physical Design, ISPD 2004
    國家/地區美國
    城市Phoenix, AZ
    期間18/04/0421/04/04

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