摘要
We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3-D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3-D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3-D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.
原文 | English |
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頁面 | 108-115 |
頁數 | 8 |
DOIs | |
出版狀態 | Published - 4月 2004 |
事件 | Proceedings of the International Symposium on Physical Design, ISPD 2004 - Phoenix, AZ, 美國 持續時間: 18 4月 2004 → 21 4月 2004 |
Conference
Conference | Proceedings of the International Symposium on Physical Design, ISPD 2004 |
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國家/地區 | 美國 |
城市 | Phoenix, AZ |
期間 | 18/04/04 → 21/04/04 |