Technology and applications of three-dimensional integration

Rafael Reif*, Chuan Seng Tan, Andy Fan, Kuan-Neng Chen, Shamik Das, Nisha Checka

*此作品的通信作者

    研究成果同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    Three-dimensional (3-D) integration holds tremendous potential to reduce global interconnect latency and power dissipation, and to improve integrated circuits (ICs) form factor. Moreover, it allows heterogeneous integration of different functional blocks (e.g., logic, memory, RF, etc) and materials (e.g., Silicon, SiGe, III-IV, etc). This paper explores the opportunities and challenges of a 3-D integration approach based on a silicon layer transfer process. It combines low temperature direct wafer bonding (Cu-to-Cu and SiO 2-to-SiO 2), high rate and selectivity silicon etching, and wafer de-bonding. A thorough description, of process integration will be given and key technological challenges will be highlighted. In addition, CAD tools for 3-D ICs design and layout are being developed. Potential 3-D applications for system-on-a-chip (SoC) and related issues will be discussed.

    原文English
    頁面261-276
    頁數16
    出版狀態Published - 10月 2004
    事件Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium - Honolulu, HI, 美國
    持續時間: 3 10月 20048 10月 2004

    Conference

    ConferenceDielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium
    國家/地區美國
    城市Honolulu, HI
    期間3/10/048/10/04

    指紋

    深入研究「Technology and applications of three-dimensional integration」主題。共同形成了獨特的指紋。

    引用此