TY - GEN
T1 - Technologies Toward Three-Dimensional Brain-Mimicking IC Architecture
AU - Chin, Albert
AU - Chen, You Da
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/3
Y1 - 2019/3
N2 - Although device downscaling will soon reach the quantum limit, the speed and power are still the hard challenges for advanced ICs. To address these speed and power issues, we pioneered the three-dimensional (3D) IC in 2004. In contrast to few interconnects of package-level 3D IC, device-level high-mobility nMOS on VLSI backend, unipolar nMOS logic with CMOS-like ultra-low DC power, narrow distribution RRAM, and high-speed ferroelectric nMOS memory are the enabling technologies toward brain-mimicking IC architecture.
AB - Although device downscaling will soon reach the quantum limit, the speed and power are still the hard challenges for advanced ICs. To address these speed and power issues, we pioneered the three-dimensional (3D) IC in 2004. In contrast to few interconnects of package-level 3D IC, device-level high-mobility nMOS on VLSI backend, unipolar nMOS logic with CMOS-like ultra-low DC power, narrow distribution RRAM, and high-speed ferroelectric nMOS memory are the enabling technologies toward brain-mimicking IC architecture.
KW - device level 3D
KW - memory
KW - unipolar logic
UR - http://www.scopus.com/inward/record.url?scp=85067786793&partnerID=8YFLogxK
U2 - 10.1109/EDTM.2019.8731323
DO - 10.1109/EDTM.2019.8731323
M3 - Conference contribution
AN - SCOPUS:85067786793
T3 - 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
SP - 472
EP - 474
BT - 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
Y2 - 12 March 2019 through 15 March 2019
ER -