A survey is presented of three techniques for the trace-driven simulation of cache designs: stack analysis methodologies that make it possible to obtain performance measures for a wide variety of cache designs from a single run of the simulator, compression algorithms specifically tailored to memory reference traces, and an approach to parallel trace-driven simulation of multiprocessor caches that dramatically reduces the simulation's synchronization and thus its running time.
|頁（從 - 到）||1042-1046|
|期刊||Winter Simulation Conference Proceedings|
|出版狀態||Published - 1 十二月 1989|
|事件||1989 Winter Simulation Conference Proceedings - WSC '89 - Washington, DC, USA|
持續時間: 4 十二月 1989 → 6 十二月 1989