Systolic building block for logic-on-logic 3D-IC implementations of convolutional neural networks

H. T. Kung, Bradley McDanel, Sai Qian Zhang, C. T. Wang, Jin Cai, C. Y. Chen, Victor C.Y. Chang, M. F. Chen, Jack Y.C. Sun, Douglas Yu

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

We present a building block architecture for systolic array 3D-IC implementations of convolutional neural network (CNN) inference. The building block can be part of a library offered by a chip design service provider to support efficient CNN implementations. We describe how the building block can form systolic arrays for implementing low-latency, energy-efficient CNN inference for models of any size, while incorporating advanced packaging features such as “logic-on-logic” 3D-IC (micro-bump/TSV, monolithic 3D or other 3D technology). We present delay and power analysis for 2D and 3D implementations, and argue that as systolic arrays scale in size, 3D implementations based on, e.g., micro-bump/TSV, lead to significant performance improvements over 2D implementations.

原文English
主出版物標題2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728103976
DOIs
出版狀態Published - 2019
事件2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
持續時間: 26 5月 201929 5月 2019

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2019-May
ISSN(列印)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
國家/地區Japan
城市Sapporo
期間26/05/1929/05/19

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