System scaling and collaborative open innovation

Jack Y.C. Sun*

*此作品的通信作者

研究成果: Conference contribution同行評審

11 引文 斯高帕斯(Scopus)

摘要

Giga trends in mobile computing, converged devices, cloud, and many other emerging applications continue to drive the growth of Si-based nano-electronics industry. A holistic approach must be taken to meet the demanding system requirements such as energy efficiency, integration density, information throughput, specialty features, and form factor. A new scaling paradigm is proposed, i.e., system scaling, by combining silicon wafer-based chip scaling and copper Through-Si-Via (TSV) 3D chip stacking to provide the ultimate energy-efficient scaling for system integration. Technically, chip scaling (Moore's Law) can be extended to provide high-density and energy-efficient transistors and Cu/low-k on-chip interconnect operated at low supply voltages for the increasing use of multiple processor cores and parallelism. In addition, Cu-TSV 3D chip stacking provides a new system integration platform to heterogeneously integrate CMOS processors, memories, and specialty functions such as sensors, actuators, and other user interfaces. It enables better system partitioning for each system component to be optimized and integrated closely together for additional power saving, higher performance, equivalent density scaling, and form factor reduction. Many challenges are ahead and there are tremendous opportunities for industry-wide collaborative open innovation in this new era of system scaling to enable the continued growth of Si-based nano-electronic industry.

原文English
主出版物標題2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers
頁面T2-T7
出版狀態Published - 2013
事件2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan
持續時間: 11 六月 201313 六月 2013

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
ISSN(列印)0743-1562

Conference

Conference2013 Symposium on VLSI Technology, VLSIT 2013
國家/地區Japan
城市Kyoto
期間11/06/1313/06/13

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