System-Level ESD-Induced Voltage Fluctuation to the Power of Integrated Circuits on System Board

Jian Hsing Lee, Karuna Nidhi, Ming Dou Ker

研究成果: Article同行評審


Based on the voltage and current waveforms, the mechanism of the system-level electrostatic-discharge (ESD) induced the voltage fluctuation to the power of integrated circuits (ICs) on system board is studied. When a contact discharge ESD test is performed at a connector pin, which is terminated with an I/O pin of an IC, not all the current from the system-level ESD may flow through the IC to the ground of the system board. So, the remaining currents can only flow through the power line of the ICs and the connection wire into the power supply to the ground. The power supply has the feedback and pulsewidth modulation circuits to regulate its output voltage. Therefore, the output current of the power supply will interact with the remnant current from the ICs on system board, resulting in the current flowing through the connection wire in the microelectronics system back and forth. Hence, the power of system board will be pulled up and down by the connection wire based on L·(dI/dt), since it acts as an inductor during the alternating current. With the voltage swinging up and down, the p-n junctions in the power domain seems to be driven into the avalanche breakdown or forwarded to generate a lot of electrons and holes inside the ICs, leading to the latch-up event at the low latch-up immunity region.

頁(從 - 到)1-7
期刊IEEE Transactions on Electromagnetic Compatibility
出版狀態Accepted/In press - 2022


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