Symmetry Incorporated Cost-Effective Architectures for Two-Dimensional Digital Filters

Lan-Da Van, I. Hung Khoo, Pei Yu Chen, Haranatha Hari C. Reddy

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)

摘要

Professor Fettweis as far back as 1977 published a paper generalizing McClellan transformation to obtain circular symmetry in 2-D and spherical, hyper-spherical symmetries in multidimensional digital filters [1]. This survey paper presents stateof-the-art two-dimensional (2-D) VLSI digital filter architectures possessing various symmetries in the filter magnitude response. Preceding the symmetry structures, a generalized formulation is given that allows the derivation of various new 2-D VLSI filter structures of any order without global broadcast. Following this, two types (namely, Type 1 [20] and Type 3 [21], [25], [26]) of cost-effective 2-D magnitude symmetry filter architectures possessing diagonal, four-fold rotational, quadrantal, and octagonal symmetries with reduced number of multipliers are given. By combining the identities of the Types-1 and 3 symmetry filter structures, multimode 2-D symmetry filters which enable the above four symmetry modes are discussed. The Type-1 and Type-3 multimode filters can result in a 65.3% cost reduction in terms of number of multipliers compared with the sum of the multipliers of the four individual Type-1 symmetry filter structures studied in this paper. Furthermore, Type-3 has shorter critical path than Type-1 multimode filter. The paper is concluded with the presentation of a 2-D filter design example and a corresponding structure.

原文English
文章編號8640217
頁(從 - 到)33-54
頁數22
期刊IEEE Circuits and Systems Magazine
19
發行號1
DOIs
出版狀態Published - 1 一月 2019

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