Switched-Capacitor-Assisted Power Gating for Ultra-Low Standby Power in CMOS Digital ICs

Sivaneswaran Sankar*, Mayank Goel, Po-Hung Chen, V. Ramgopal Rao, Maryam Shojaei Baghini

*此作品的通信作者

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

This article presents Switched-Capacitor assisted Power Gating (SwCap PG) for reducing the leakage currents of large digital circuits. For the first time, PG switch is biased in the super turn-off and the super turn-on mode during the off-state and the on-state, respectively. A simple switched-capacitor network reconfigures and biases the PG switch in four different possible states with low area and power overhead. During the super turn-off, voltage stress is avoided in the PG switch when the circuit load uses supply voltage equal to the nominal V-DD in a given technology, and maximum possible leakage current reduction is achieved by the optimal biasing of the gate voltage. The proposed SwCap PG is experimentally validated in the 180nm CMOS technology. Measurement results of CMOS SwCap PG show that leakage current and R-ON reduce by 186-226x and 18% respectively, as compared to the conventional PG. An alternate solution for SwCap network using MEMS devices as the switching elements is implemented for additional benefits. Measurement results of MEMS SwCap PG show that leakage current and R-ON reduce by 172x and 26% respectively, compared to the conventional PG. Finally, the applicability of the SwCap PG in the nano-scale CMOS technologies is addressed.

原文English
文章編號9169784
頁(從 - 到)4281-4294
頁數14
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
67
發行號12
DOIs
出版狀態Published - 12月 2020

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