Switchable NAND and NOR logic computing in single triple-gate monolayer MoS2n-FET

Yun Yan Chung; Chao Ching Cheng; Bo Kai Kang; Wei Chen Chueh; Shih Yun Wang; Chen Han Chou; Terry Y.T. Hung; Shin Yuan Wang; Wen Hao Chang; Lain Jong Li; Chao Hsin Chien

doi:10.1109/IEDM13553.2020.9372072

Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET

Yun Yan Chung, Chao Ching Cheng^*, Bo Kai Kang, Wei Chen Chueh, Shih Yun Wang, Chen Han Chou, Terry Y.T. Hung, Shin Yuan Wang, Wen Hao Chang, Lain Jong Li, Chao Hsin Chien

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.

原文	English
主出版物標題	2020 IEEE International Electron Devices Meeting, IEDM 2020
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	40.3.1-40.3.4
ISBN（電子）	9781728188881
DOIs	https://doi.org/10.1109/IEDM13553.2020.9372072
出版狀態	Published - 12 12月 2020
事件	66th Annual IEEE International Electron Devices Meeting, IEDM 2020 - Virtual, San Francisco, 美國持續時間: 12 12月 2020 → 18 12月 2020

出版系列

名字	Technical Digest - International Electron Devices Meeting, IEDM
卷	2020-December
ISSN（列印）	0163-1918

Conference

Conference	66th Annual IEEE International Electron Devices Meeting, IEDM 2020
國家/地區	美國
城市	Virtual, San Francisco
期間	12/12/20 → 18/12/20

存取文件

10.1109/IEDM13553.2020.9372072

其它文件與鏈接

Link to publication in Scopus

引用此

Chung, Y. Y., Cheng, C. C., Kang, B. K., Chueh, W. C., Wang, S. Y., Chou, C. H., Hung, T. Y. T., Wang, S. Y., Chang, W. H., Li, L. J., & Chien, C. H. (2020). Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET. 於 2020 IEEE International Electron Devices Meeting, IEDM 2020 (頁 40.3.1-40.3.4). 文章 9372072 (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2020-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM13553.2020.9372072

@inproceedings{df01314556cb4708a6fbb8e92c697619,

title = "Switchable NAND and NOR logic computing in single triple-gate monolayer MoS2n-FET",

abstract = "We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.",

author = "Chung, {Yun Yan} and Cheng, {Chao Ching} and Kang, {Bo Kai} and Chueh, {Wei Chen} and Wang, {Shih Yun} and Chou, {Chen Han} and Hung, {Terry Y.T.} and Wang, {Shin Yuan} and Chang, {Wen Hao} and Li, {Lain Jong} and Chien, {Chao Hsin}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 66th Annual IEEE International Electron Devices Meeting, IEDM 2020 ; Conference date: 12-12-2020 Through 18-12-2020",

year = "2020",

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doi = "10.1109/IEDM13553.2020.9372072",

language = "English",

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Chung, YY, Cheng, CC, Kang, BK, Chueh, WC, Wang, SY, Chou, CH, Hung, TYT, Wang, SY, Chang, WH, Li, LJ & Chien, CH 2020, Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET. 於 2020 IEEE International Electron Devices Meeting, IEDM 2020., 9372072, Technical Digest - International Electron Devices Meeting, IEDM, 卷 2020-December, Institute of Electrical and Electronics Engineers Inc., 頁 40.3.1-40.3.4, 66th Annual IEEE International Electron Devices Meeting, IEDM 2020, Virtual, San Francisco, 美國, 12/12/20. https://doi.org/10.1109/IEDM13553.2020.9372072

Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET. / Chung, Yun Yan; Cheng, Chao Ching; Kang, Bo Kai 等.
2020 IEEE International Electron Devices Meeting, IEDM 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 40.3.1-40.3.4 9372072 (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2020-December).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Switchable NAND and NOR logic computing in single triple-gate monolayer MoS2n-FET

AU - Chung, Yun Yan

AU - Cheng, Chao Ching

AU - Kang, Bo Kai

AU - Chueh, Wei Chen

AU - Wang, Shih Yun

AU - Chou, Chen Han

AU - Hung, Terry Y.T.

AU - Wang, Shin Yuan

AU - Chang, Wen Hao

AU - Li, Lain Jong

AU - Chien, Chao Hsin

PY - 2020/12/12

Y1 - 2020/12/12

N2 - We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.

AB - We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.

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M3 - Conference contribution

AN - SCOPUS:85102919144

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 40.3.1-40.3.4

BT - 2020 IEEE International Electron Devices Meeting, IEDM 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 66th Annual IEEE International Electron Devices Meeting, IEDM 2020

Y2 - 12 December 2020 through 18 December 2020

ER -

Chung YY, Cheng CC, Kang BK, Chueh WC, Wang SY, Chou CH 等. Switchable NAND and NOR logic computing in single triple-gate monolayer MoS₂n-FET. 於 2020 IEEE International Electron Devices Meeting, IEDM 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 40.3.1-40.3.4. 9372072. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM13553.2020.9372072