Switchable NAND and NOR logic computing in single triple-gate monolayer MoS2n-FET

Yun Yan Chung, Chao Ching Cheng*, Bo Kai Kang, Wei Chen Chueh, Shih Yun Wang, Chen Han Chou, Terry Y.T. Hung, Shin Yuan Wang, Wen Hao Chang, Lain Jong Li, Chao Hsin Chien

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

We propose a novel triple-gated single transistor comprising monolayer MoS2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS2 n-FET and switchable easily through top-gate bias setting (VLOW / VHIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.

原文English
主出版物標題2020 IEEE International Electron Devices Meeting, IEDM 2020
發行者Institute of Electrical and Electronics Engineers Inc.
頁面40.3.1-40.3.4
ISBN(電子)9781728188881
DOIs
出版狀態Published - 12 十二月 2020
事件66th Annual IEEE International Electron Devices Meeting, IEDM 2020 - Virtual, San Francisco, United States
持續時間: 12 十二月 202018 十二月 2020

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2020-December
ISSN(列印)0163-1918

Conference

Conference66th Annual IEEE International Electron Devices Meeting, IEDM 2020
國家/地區United States
城市Virtual, San Francisco
期間12/12/2018/12/20

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