Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si

Chia Chen Wan; Guang Li Luo; Shu Han Hsu; Kuo Dong Hung; Chun Lin Chu; Tuo-Hung Hou; Chun Jun Su; Szu Hung Chen; Wen Fa Wu; Wen Kuan Yeh

doi:10.1109/SNW.2016.7578017

Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si

Chia Chen Wan, Guang Li Luo, Shu Han Hsu, Kuo Dong Hung, Chun Lin Chu, Tuo-Hung Hou, Chun Jun Su, Szu Hung Chen, Wen Fa Wu, Wen Kuan Yeh

研究成果: Conference contribution › 同行評審

摘要

Replacing Si channel with selective epi-Ge in mainstream bulk FinFETs can be a cost-effective solution for sub-7 nm node, but is facing severe challenges because of poor isolation to Si substrates. We demonstrate a suspended Ge gate-all-around (GAA) nanowire nFET (nNWFET) technology with junction isolation on bulk Si. Because of the low junction leakage provided by an embedded Si junction, improved electrostatics of GAA structure utilizing surrounding high-mobility 111 surfaces, and a dislocation-free channel by selectively removing the defective Ge/Si interface, a high current on/off ratio (I _ON /I _OFF ) of 5×10 ⁵ , which is comparable to the state-of-the-art Ge nFETs on Ge-on-insulator (GeOI), is first demonstrated using a bulk FinFET-compatible process.

原文	English
主出版物標題	2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	130-131
頁數	2
ISBN（電子）	9781509007264
DOIs	https://doi.org/10.1109/SNW.2016.7578017
出版狀態	Published - 13 6月 2016
事件	21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 - Honolulu, United States 持續時間: 12 6月 2016 → 13 6月 2016

出版系列

名字	2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

Conference

Conference	21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
國家/地區	United States
城市	Honolulu
期間	12/06/16 → 13/06/16

存取文件

10.1109/SNW.2016.7578017

其它文件與鏈接

Link to publication in Scopus

引用此

Wan, C. C., Luo, G. L., Hsu, S. H., Hung, K. D., Chu, C. L., Hou, T-H., Su, C. J., Chen, S. H., Wu, W. F., & Yeh, W. K. (2016). Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si. 於 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016 (頁 130-131). [7578017] (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SNW.2016.7578017

@inproceedings{a632a8e5725f42cfa2cf630cd245dc59,

title = "Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si",

abstract = " Replacing Si channel with selective epi-Ge in mainstream bulk FinFETs can be a cost-effective solution for sub-7 nm node, but is facing severe challenges because of poor isolation to Si substrates. We demonstrate a suspended Ge gate-all-around (GAA) nanowire nFET (nNWFET) technology with junction isolation on bulk Si. Because of the low junction leakage provided by an embedded Si junction, improved electrostatics of GAA structure utilizing surrounding high-mobility 111 surfaces, and a dislocation-free channel by selectively removing the defective Ge/Si interface, a high current on/off ratio (I ON /I OFF ) of 5×10 5 , which is comparable to the state-of-the-art Ge nFETs on Ge-on-insulator (GeOI), is first demonstrated using a bulk FinFET-compatible process. ",

author = "Wan, {Chia Chen} and Luo, {Guang Li} and Hsu, {Shu Han} and Hung, {Kuo Dong} and Chu, {Chun Lin} and Tuo-Hung Hou and Su, {Chun Jun} and Chen, {Szu Hung} and Wu, {Wen Fa} and Yeh, {Wen Kuan}",

year = "2016",

month = jun,

day = "13",

doi = "10.1109/SNW.2016.7578017",

language = "English",

series = "2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "130--131",

booktitle = "2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016",

address = "United States",

note = "null ; Conference date: 12-06-2016 Through 13-06-2016",

}

Wan, CC, Luo, GL, Hsu, SH, Hung, KD, Chu, CL, Hou, T-H, Su, CJ, Chen, SH, Wu, WF & Yeh, WK 2016, Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si. 於 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016., 7578017, 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016, Institute of Electrical and Electronics Engineers Inc., 頁 130-131, 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016, Honolulu, United States, 12/06/16. https://doi.org/10.1109/SNW.2016.7578017

Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si. / Wan, Chia Chen; Luo, Guang Li; Hsu, Shu Han 等.

2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 130-131 7578017 (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si

AU - Wan, Chia Chen

AU - Luo, Guang Li

AU - Hsu, Shu Han

AU - Hung, Kuo Dong

AU - Chu, Chun Lin

AU - Hou, Tuo-Hung

AU - Su, Chun Jun

AU - Chen, Szu Hung

AU - Wu, Wen Fa

AU - Yeh, Wen Kuan

PY - 2016/6/13

Y1 - 2016/6/13

N2 - Replacing Si channel with selective epi-Ge in mainstream bulk FinFETs can be a cost-effective solution for sub-7 nm node, but is facing severe challenges because of poor isolation to Si substrates. We demonstrate a suspended Ge gate-all-around (GAA) nanowire nFET (nNWFET) technology with junction isolation on bulk Si. Because of the low junction leakage provided by an embedded Si junction, improved electrostatics of GAA structure utilizing surrounding high-mobility 111 surfaces, and a dislocation-free channel by selectively removing the defective Ge/Si interface, a high current on/off ratio (I ON /I OFF ) of 5×10 5 , which is comparable to the state-of-the-art Ge nFETs on Ge-on-insulator (GeOI), is first demonstrated using a bulk FinFET-compatible process.

AB - Replacing Si channel with selective epi-Ge in mainstream bulk FinFETs can be a cost-effective solution for sub-7 nm node, but is facing severe challenges because of poor isolation to Si substrates. We demonstrate a suspended Ge gate-all-around (GAA) nanowire nFET (nNWFET) technology with junction isolation on bulk Si. Because of the low junction leakage provided by an embedded Si junction, improved electrostatics of GAA structure utilizing surrounding high-mobility 111 surfaces, and a dislocation-free channel by selectively removing the defective Ge/Si interface, a high current on/off ratio (I ON /I OFF ) of 5×10 5 , which is comparable to the state-of-the-art Ge nFETs on Ge-on-insulator (GeOI), is first demonstrated using a bulk FinFET-compatible process.

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U2 - 10.1109/SNW.2016.7578017

DO - 10.1109/SNW.2016.7578017

M3 - Conference contribution

AN - SCOPUS:84994738788

T3 - 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

SP - 130

EP - 131

BT - 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 12 June 2016 through 13 June 2016

ER -

Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si

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