Suppressing Threshold Voltage Drift in Sub-2 nm In2O3Transistors with Improved Thermal Stability

Kris K.H. Lin, Li Cheng Teng, Tzu Ting Weng, Tzu Jie Lin, Jian Cun Lin, Shin Yuan Wang, Po Hsun Ho, Wei Yen Woon, Chi Chung Kei, Tsung Te Chou, Chao Hsin Chien*, Der Hsien Lien*

*此作品的通信作者

研究成果: Article同行評審

摘要

Ultrathin In2O3 films with a thickness of less than 2 nm have emerged as highly intriguing semiconductor channels owing to their exceptional electronic properties. However, their process reliability, particularly the challenge of threshold voltage ( $V_{\text {T}}$ ) drift during gate-stack processing, hinders their potential applications in back-end-of-line (BEOL). This study explores the $V_{\text {T}}$ shift induced by stacked HfO2, showing both thermal atomic layer deposition (T-ALD) and plasma-enhanced atomic layer deposition (PE-ALD) cause significant $V_{\text {T}}$ shift in ultrathin In2O3. To mitigate $V_{\text {T}}$ shift, we introduce a pre-dielectric stacking, solution-based treatment, which can effectively passivate oxygen-related defects in ultrathin In2O3, maintaining $V_{\text {T}}$ without adversely affecting electrical properties. Utilizing this technique, we have successfully demonstrated the first top-gate In2O3 transistor without the requirement of post-fabrication annealing to uphold the on/off ratio. The developed top-gate device also exhibits superior thermal stability, suggesting its potential for future monolithic 3D integration applications.

原文English
頁(從 - 到)60-63
頁數4
期刊Ieee Electron Device Letters
45
發行號1
DOIs
出版狀態Published - 1 1月 2024

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