Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget

Shu Han Whi; Yu-Min Lee

doi:10.1109/VDAT.2011.5783562

Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget

Shu Han Whi^*, Yu-Min Lee

^*此作品的通信作者

電機工程學系

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

Few of existing works on power reduction in 3D ICs discuss the ability of supply voltage scaling techniques for power optimization. In this work, a supply voltage assignment based method for minimizing the power consumption of 3D ICs is presented. The proposed approach includes three major headings: (1) 3D IC Voltage Assignment for power reduction with including three factorssensitivity, proximity effect and level shifter (LS) budget; (2) 3D Electro-Thermal Analysis for the temperature distribution of 3D IC; (3) Thermal Aware Static Timing Analysis for thermal-related delay values of functional gates. The experimental results have shown a great power reduction by the proposed method.

原文	English
主出版物標題	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
頁面	418-421
頁數	4
DOIs	https://doi.org/10.1109/VDAT.2011.5783562
出版狀態	Published - 2011
事件	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan 持續時間: 25 4月 2011 → 28 4月 2011

出版系列

名字	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
國家/地區	Taiwan
城市	Hsinchu
期間	25/04/11 → 28/04/11

存取文件

10.1109/VDAT.2011.5783562

其它文件與鏈接

Link to publication in Scopus

引用此

Whi, S. H., & Lee, Y.-M. (2011). Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget. 於 Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (頁 418-421). 文章 5783562 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). https://doi.org/10.1109/VDAT.2011.5783562

@inproceedings{4e902844957c4c10b305a7b39e7baef4,

title = "Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget",

abstract = "Few of existing works on power reduction in 3D ICs discuss the ability of supply voltage scaling techniques for power optimization. In this work, a supply voltage assignment based method for minimizing the power consumption of 3D ICs is presented. The proposed approach includes three major headings: (1) 3D IC Voltage Assignment for power reduction with including three factorssensitivity, proximity effect and level shifter (LS) budget; (2) 3D Electro-Thermal Analysis for the temperature distribution of 3D IC; (3) Thermal Aware Static Timing Analysis for thermal-related delay values of functional gates. The experimental results have shown a great power reduction by the proposed method.",

author = "Whi, {Shu Han} and Yu-Min Lee",

year = "2011",

doi = "10.1109/VDAT.2011.5783562",

language = "English",

isbn = "9781424484997",

series = "Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011",

pages = "418--421",

booktitle = "Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011",

note = "2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 ; Conference date: 25-04-2011 Through 28-04-2011",

}

Whi, SH & Lee, Y-M 2011, Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget. 於 Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783562, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, 頁 418-421, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, Taiwan, 25/04/11. https://doi.org/10.1109/VDAT.2011.5783562

Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget. / Whi, Shu Han; Lee, Yu-Min.
Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 418-421 5783562 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget

AU - Whi, Shu Han

AU - Lee, Yu-Min

PY - 2011

Y1 - 2011

N2 - Few of existing works on power reduction in 3D ICs discuss the ability of supply voltage scaling techniques for power optimization. In this work, a supply voltage assignment based method for minimizing the power consumption of 3D ICs is presented. The proposed approach includes three major headings: (1) 3D IC Voltage Assignment for power reduction with including three factorssensitivity, proximity effect and level shifter (LS) budget; (2) 3D Electro-Thermal Analysis for the temperature distribution of 3D IC; (3) Thermal Aware Static Timing Analysis for thermal-related delay values of functional gates. The experimental results have shown a great power reduction by the proposed method.

AB - Few of existing works on power reduction in 3D ICs discuss the ability of supply voltage scaling techniques for power optimization. In this work, a supply voltage assignment based method for minimizing the power consumption of 3D ICs is presented. The proposed approach includes three major headings: (1) 3D IC Voltage Assignment for power reduction with including three factorssensitivity, proximity effect and level shifter (LS) budget; (2) 3D Electro-Thermal Analysis for the temperature distribution of 3D IC; (3) Thermal Aware Static Timing Analysis for thermal-related delay values of functional gates. The experimental results have shown a great power reduction by the proposed method.

UR - http://www.scopus.com/inward/record.url?scp=79959516955&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2011.5783562

DO - 10.1109/VDAT.2011.5783562

M3 - Conference contribution

AN - SCOPUS:79959516955

SN - 9781424484997

T3 - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

SP - 418

EP - 421

BT - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

T2 - 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Y2 - 25 April 2011 through 28 April 2011

ER -

Whi SH, Lee YM. Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget. 於 Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 418-421. 5783562. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). doi: 10.1109/VDAT.2011.5783562

Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget

摘要

出版系列

Conference

存取文件

其它文件與鏈接

指紋

引用此