Supply voltage assignment for power reduction in 3D ICs considering thermal effect and level shifter budget

Shu Han Whi*, Yu-Min Lee

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

Few of existing works on power reduction in 3D ICs discuss the ability of supply voltage scaling techniques for power optimization. In this work, a supply voltage assignment based method for minimizing the power consumption of 3D ICs is presented. The proposed approach includes three major headings: (1) 3D IC Voltage Assignment for power reduction with including three factorssensitivity, proximity effect and level shifter (LS) budget; (2) 3D Electro-Thermal Analysis for the temperature distribution of 3D IC; (3) Thermal Aware Static Timing Analysis for thermal-related delay values of functional gates. The experimental results have shown a great power reduction by the proposed method.

原文English
主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
頁面418-421
頁數4
DOIs
出版狀態Published - 28 六月 2011
事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
持續時間: 25 四月 201128 四月 2011

出版系列

名字Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
國家/地區Taiwan
城市Hsinchu
期間25/04/1128/04/11

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