Substrate noise suppression technique for power integrity of TSV 3D integration

Po Jen Yang; Po-Tsang Huang; Wei Hwang

doi:10.1109/ISCAS.2012.6272024

Substrate noise suppression technique for power integrity of TSV 3D integration

Po Jen Yang^*, Po-Tsang Huang, Wei Hwang

^*此作品的通信作者

國際半導體產業學院

研究成果: Paper › 同行評審

5 引文斯高帕斯（Scopus）

摘要

In this paper, a substrate noise suppression technique is proposed for the power integrity of TSV 3D integrations. This substrate noise suppression technique reduces both substrate and TSV coupling noises using active substrate decouplers (ASDs) to absorb the substrate noise current. Additionally, the ASD placing is also presented to suppress noises effectively for different 3D structures. For a processor-memory stacking integration, the ground bouncing noises can be reduced by 44.1% via the noise suppression technique. The proposed substrate noise suppression technique can enhance the power integrity of TSV 3D-ICs by reducing the coupling substrate noises.

原文	English
頁面	3274-3277
頁數	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6272024
出版狀態	Published - 2012
事件	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, 韓國持續時間: 20 5月 2012 → 23 5月 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家/地區	韓國
城市	Seoul
期間	20/05/12 → 23/05/12

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10.1109/ISCAS.2012.6272024

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Link to publication in Scopus

引用此

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title = "Substrate noise suppression technique for power integrity of TSV 3D integration",

abstract = "In this paper, a substrate noise suppression technique is proposed for the power integrity of TSV 3D integrations. This substrate noise suppression technique reduces both substrate and TSV coupling noises using active substrate decouplers (ASDs) to absorb the substrate noise current. Additionally, the ASD placing is also presented to suppress noises effectively for different 3D structures. For a processor-memory stacking integration, the ground bouncing noises can be reduced by 44.1% via the noise suppression technique. The proposed substrate noise suppression technique can enhance the power integrity of TSV 3D-ICs by reducing the coupling substrate noises.",

author = "Yang, {Po Jen} and Po-Tsang Huang and Wei Hwang",

year = "2012",

doi = "10.1109/ISCAS.2012.6272024",

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note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

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AU - Yang, Po Jen

AU - Huang, Po-Tsang

AU - Hwang, Wei

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AB - In this paper, a substrate noise suppression technique is proposed for the power integrity of TSV 3D integrations. This substrate noise suppression technique reduces both substrate and TSV coupling noises using active substrate decouplers (ASDs) to absorb the substrate noise current. Additionally, the ASD placing is also presented to suppress noises effectively for different 3D structures. For a processor-memory stacking integration, the ground bouncing noises can be reduced by 44.1% via the noise suppression technique. The proposed substrate noise suppression technique can enhance the power integrity of TSV 3D-ICs by reducing the coupling substrate noises.

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DO - 10.1109/ISCAS.2012.6272024

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T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

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Substrate noise suppression technique for power integrity of TSV 3D integration

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