Sub-word and reduced-width booth multipliers for DSP applications

Meng Hung Tsai*, Yi Ting Chen, Wen Sheng Cheng, Jun Xian Teng, Shyh-Jye Jou

*此作品的通信作者

研究成果: Conference article同行評審

摘要

In this paper, based on the low-power version of parallel Booth multiplier we will show one novel sub-word parallel (SWP) multiplier and one low-error reduced-width multiplier. In the new SWP multiplier, it can finish one n by n multiplication or two n/2 by n/2 multiplications or the multiplication of two n/2 complex numbers in the same architecture. In the low-error reduced-width multiplier, an input number dependent compensation vector is derived that is superior to other proposed results in error performance and operation speed. The implementation results of 16 by 16 to 16 case show that the area is 50.67% and the critical path delay is 66.18% of the original Booth multiplier.

原文English
頁(從 - 到)III/575-III/578
期刊Proceedings - IEEE International Symposium on Circuits and Systems
3
DOIs
出版狀態Published - 2002
事件2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
持續時間: 26 5月 200229 5月 2002

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