Sub-sampling charge pump and random pulsewidth matching technique for frequency synthesizer

Te Wen Liao, Jun Ren Su, Chung-Chih Hung

研究成果: Conference contribution同行評審

摘要

This paper presents a frequency synthesizer system with random pulsewidth matching technique and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of-114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below-74 dBc.

原文English
主出版物標題2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
頁面1035-1038
頁數4
DOIs
出版狀態Published - 2013
事件2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 - Columbus, OH, United States
持續時間: 4 8月 20137 8月 2013

出版系列

名字Midwest Symposium on Circuits and Systems
ISSN(列印)1548-3746

Conference

Conference2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
國家/地區United States
城市Columbus, OH
期間4/08/137/08/13

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