@inproceedings{0385f441c36040c8a1417e046a6161c6,
title = "Sub-sampling charge pump and random pulsewidth matching technique for frequency synthesizer",
abstract = "This paper presents a frequency synthesizer system with random pulsewidth matching technique and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of-114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below-74 dBc.",
keywords = "PLL, Synthesizer, low spur",
author = "Liao, {Te Wen} and Su, {Jun Ren} and Chung-Chih Hung",
year = "2013",
doi = "10.1109/MWSCAS.2013.6674829",
language = "English",
isbn = "9781479900664",
series = "Midwest Symposium on Circuits and Systems",
pages = "1035--1038",
booktitle = "2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013",
note = "2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 ; Conference date: 04-08-2013 Through 07-08-2013",
}