Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line

C. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, Shyh-Jye Jou, P. H. Chen, Hung-Ming Chen, B. D. Rong, K. Itoh

研究成果: Conference contribution同行評審

摘要

A 0.45 V 28-nm 32-Kb SRAM with multi-power-supply low-power circuits, such as a cross-point 5T with built-in Y-line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.

原文English
主出版物標題Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
發行者Institute of Electrical and Electronics Engineers Inc.
頁面227-230
頁數4
ISBN(電子)9781728151069
DOIs
出版狀態Published - 11月 2019
事件15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China
持續時間: 4 11月 20196 11月 2019

出版系列

名字Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
國家/地區China
城市Macao
期間4/11/196/11/19

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