@inproceedings{f20da81bf35b42c1b0f13d58dbc34bd8,
title = "Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 v Cross-Point-5T Cell and Built-in Y-Line",
abstract = "A 0.45 V 28-nm 32-Kb SRAM with multi-power-supply low-power circuits, such as a cross-point 5T with built-in Y-line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.",
keywords = "5T bit (memory) cell, gate-boosting driver, low-power array, Sub-0.5 V SRAM",
author = "He, {C. Y.} and Tang, {K. H.} and Chen, {T. S.} and Chang, {K. Y.} and Lin, {C. H.} and K. Sato and Shyh-Jye Jou and Chen, {P. H.} and Hung-Ming Chen and Rong, {B. D.} and K. Itoh",
year = "2019",
month = nov,
doi = "10.1109/A-SSCC47793.2019.9056897",
language = "English",
series = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "227--230",
booktitle = "Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019",
address = "美國",
note = "15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 ; Conference date: 04-11-2019 Through 06-11-2019",
}