Sub 50-nm FinFET: PMOS

Xuejue Huang; Wen Chin Lee; Charles Kuo; Digh Hisamoto; Leland Chang; Jakub Kedzierski; Erik Anderson; Hideki Takeuchi; Yang Kyu Choi; Kazuya Asano; Vivek Subramanian; Tsu Jae King; Jeffrey Bokor; Chen-Ming Hu

doi:10.1109/IEDM.1999.823848

Sub 50-nm FinFET: PMOS

Xuejue Huang^*, Wen Chin Lee, Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Yang Kyu Choi, Kazuya Asano, Vivek Subramanian, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

477 引文斯高帕斯（Scopus）

摘要

High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. 45 nm gate-length PMOS FinFET has an I_dsat of 410 μA/μm (or 820 μA/μm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

原文	English
頁（從 - 到）	67-70
頁數	4
期刊	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.1999.823848
出版狀態	Published - 1999
事件	1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA 持續時間: 5 12月 1999 → 8 12月 1999

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10.1109/IEDM.1999.823848

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@article{c7c7be78b1ea4483b39c152ae9a64804,

title = "Sub 50-nm FinFET: PMOS",

abstract = "High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. 45 nm gate-length PMOS FinFET has an Idsat of 410 μA/μm (or 820 μA/μm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.",

author = "Xuejue Huang and Lee, {Wen Chin} and Charles Kuo and Digh Hisamoto and Leland Chang and Jakub Kedzierski and Erik Anderson and Hideki Takeuchi and Choi, {Yang Kyu} and Kazuya Asano and Vivek Subramanian and King, {Tsu Jae} and Jeffrey Bokor and Chen-Ming Hu",

year = "1999",

doi = "10.1109/IEDM.1999.823848",

language = "English",

pages = "67--70",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "1999 IEEE International Devices Meeting (IEDM) ; Conference date: 05-12-1999 Through 08-12-1999",

}

TY - JOUR

T1 - Sub 50-nm FinFET

T2 - 1999 IEEE International Devices Meeting (IEDM)

AU - Huang, Xuejue

AU - Lee, Wen Chin

AU - Kuo, Charles

AU - Hisamoto, Digh

AU - Chang, Leland

AU - Kedzierski, Jakub

AU - Anderson, Erik

AU - Takeuchi, Hideki

AU - Choi, Yang Kyu

AU - Asano, Kazuya

AU - Subramanian, Vivek

AU - King, Tsu Jae

AU - Bokor, Jeffrey

AU - Hu, Chen-Ming

PY - 1999

Y1 - 1999

N2 - High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. 45 nm gate-length PMOS FinFET has an Idsat of 410 μA/μm (or 820 μA/μm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

AB - High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. 45 nm gate-length PMOS FinFET has an Idsat of 410 μA/μm (or 820 μA/μm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

UR - http://www.scopus.com/inward/record.url?scp=0033329310&partnerID=8YFLogxK

U2 - 10.1109/IEDM.1999.823848

DO - 10.1109/IEDM.1999.823848

M3 - Conference article

AN - SCOPUS:0033329310

SN - 0163-1918

SP - 67

EP - 70

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

Y2 - 5 December 1999 through 8 December 1999

ER -

Sub 50-nm FinFET: PMOS

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