Sub-20nm CMOS FinFET technologies

Yang Kyu Choi; Nick Lindert; Peiqi Xuan; Stephen Tang; Daewon Ha; Erik Anderson; Tsu Jae King; Jeffrey Bokor; Chen-Ming Hu

doi:10.1109/IEDM.2001.979526

Sub-20nm CMOS FinFET technologies

Yang Kyu Choi, Nick Lindert, Peiqi Xuan, Stephen Tang^*, Daewon Ha, Erik Anderson, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

193 引文斯高帕斯（Scopus）

摘要

A simplified fabrication process for sub-20nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET [1][2]. Two different patterning approaches: e-beam lithography and spacer lithography, are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improves drive current.

原文	English
頁（從 - 到）	421-424
頁數	4
期刊	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2001.979526
出版狀態	Published - 12月 2001
事件	IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, 美國持續時間: 2 12月 2001 → 5 12月 2001

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10.1109/IEDM.2001.979526

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title = "Sub-20nm CMOS FinFET technologies",

abstract = "A simplified fabrication process for sub-20nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET [1][2]. Two different patterning approaches: e-beam lithography and spacer lithography, are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improves drive current.",

author = "Choi, {Yang Kyu} and Nick Lindert and Peiqi Xuan and Stephen Tang and Daewon Ha and Erik Anderson and King, {Tsu Jae} and Jeffrey Bokor and Chen-Ming Hu",

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doi = "10.1109/IEDM.2001.979526",

language = "English",

pages = "421--424",

journal = "Technical Digest - International Electron Devices Meeting",

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TY - JOUR

T1 - Sub-20nm CMOS FinFET technologies

AU - Choi, Yang Kyu

AU - Lindert, Nick

AU - Xuan, Peiqi

AU - Tang, Stephen

AU - Ha, Daewon

AU - Anderson, Erik

AU - King, Tsu Jae

AU - Bokor, Jeffrey

AU - Hu, Chen-Ming

PY - 2001/12

Y1 - 2001/12

N2 - A simplified fabrication process for sub-20nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET [1][2]. Two different patterning approaches: e-beam lithography and spacer lithography, are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improves drive current.

AB - A simplified fabrication process for sub-20nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET [1][2]. Two different patterning approaches: e-beam lithography and spacer lithography, are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improves drive current.

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U2 - 10.1109/IEDM.2001.979526

DO - 10.1109/IEDM.2001.979526

M3 - Conference article

AN - SCOPUS:0035717948

SN - 0163-1918

SP - 421

EP - 424

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting IEDM 2001

Y2 - 2 December 2001 through 5 December 2001

ER -

Sub-20nm CMOS FinFET technologies

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