Sub-10 nm Top Width Nanowire InGaAs Gate-All-Around MOSFETs with Improved Subthreshold Characteristics and Device Reliability

Hua Lun Ko, Quang Ho Luc, Ping Huang, Jing Yuan Wu, Si Meng Chen, Nhan Ai Tran, Heng Tung Hsu, Edward Yi Chang*

*此作品的通信作者

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

In this article, sub-10 nm top width nanowire In0.53Ga0.47As gate-All-Around (GAA) MOSFETs with improved subthreshold characteristics and reliability are demonstrated. These devices exhibit a significant improvement in the subthreshold performances with subthreshold swing (SS) of 70 mV/dec, drain induced barrier lowering (DIBL) of 46 mV/V, and off-current (Ioff) of 1.6×10-4 uA/um for InGaAs GAA MOSFETs. Effective control of short channel effects (SCEs) is confirmed by the error bar of statistical variation analysis. Under gate bias stress, a low degradation of SS and threshold voltage (Vth) shift has been achieved due to N2 RP treatment of the InGaAs GAA MOSFETs. The superior performance can be attributed to the strong electrostatic control and high quality of high-/InGaAs interface, originating from shrinking nanowire width and RP passivation effects. These results show the developed GAA MOSFET devices have good potential for future low-power high-switching speed CMOS logic applications.

原文English
頁(從 - 到)188-191
頁數4
期刊IEEE Journal of the Electron Devices Society
10
DOIs
出版狀態Published - 8 2月 2022

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