@inproceedings{45751ee424f74c6ca8fc95c776a54fd3,
title = "Study on latchup path between HV-LDMOS and LVCMOS in a 0.16-μm 30-V/1.8-V BCD technology",
abstract = "The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30- V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.",
author = "Dai, {Chia Tsen} and Ming-Dou Ker and Jou, {Yeh Ning} and Huang, {Shao Chang} and Lin, {Geeng Lih} and Lee, {Jian Hsing}",
year = "2018",
month = sep,
day = "23",
doi = "10.23919/EOS/ESD.2018.8509772",
language = "English",
series = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings",
publisher = "ESD Association",
booktitle = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2018",
note = "40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018 ; Conference date: 23-09-2018 Through 28-09-2018",
}