Study on latchup path between HV-LDMOS and LVCMOS in a 0.16-μm 30-V/1.8-V BCD technology

Chia Tsen Dai, Ming-Dou Ker, Yeh Ning Jou, Shao Chang Huang, Geeng Lih Lin, Jian Hsing Lee

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

The latchup path between high-voltage (HV) PMOS and low-voltage (LV) PMOS in a 0.16-μm 30- V/1.8-V bipolar-CMOS-DMOS (BCD) technology is studied. From the experiment results on silicon chip, this path can be easily induced into latchup state during the current-trigger latchup test. Therefore, the related layout rules should be carefully specified to avoid such HV-to-LV cross-domain latchup issue.

原文English
主出版物標題Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2018
發行者ESD Association
頁數6
ISBN(電子)1585373028
DOIs
出版狀態Published - 23 9月 2018
事件40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018 - Reno, United States
持續時間: 23 9月 201828 9月 2018

出版系列

名字Electrical Overstress/Electrostatic Discharge Symposium Proceedings
2018-September
ISSN(列印)0739-5159

Conference

Conference40th Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2018
國家/地區United States
城市Reno
期間23/09/1828/09/18

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