Study of the mesa etched tri-gate InAs HEMTs with extremely low SS for low-power logic applications

Yueh Chin Lin*, Jing Neng Yao, Hisang Hua Hsu, Ying Chieh Wong, Chi Yi Huang, Heng-Tung Hsu, Hiroshi Iwai, Edward Yi Chang

*此作品的通信作者

研究成果: Paper同行評審

摘要

InAs HEMTs with a mesa etch structure that connects the Schottky gate through mesa sidewall with InAlAs layers were fabricated. The gate metal connection to the InAlAs layers increases the positive potential of the channel region through the gate bias, resulting in a steep SS due to a positive potential feedback. The mesa etch InAs HEMT shows an excellent performance with an extremely low minimum SS value of 46 mV/decade with the high G m, max /SS of 33 and a high Ion/Ioff ratio of 6.6×104 at Vds = 1V.

原文American English
頁面1-3
頁數3
DOIs
出版狀態Published - 29 5月 2018
事件2018 China Semiconductor Technology International Conference, CSTIC 2018 - Shanghai, China
持續時間: 11 3月 201812 3月 2018

Conference

Conference2018 China Semiconductor Technology International Conference, CSTIC 2018
國家/地區China
城市Shanghai
期間11/03/1812/03/18

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