Study of the mesa etched tri-gate InAs HEMTs with extremely low SS for low-power logic applications

Yueh Chin Lin; Jing Neng Yao; Hisang Hua Hsu; Ying Chieh Wong; Chi Yi Huang; Heng-Tung Hsu; Hiroshi Iwai; Edward Yi Chang

doi:10.1109/CSTIC.2018.8369315

Study of the mesa etched tri-gate InAs HEMTs with extremely low SS for low-power logic applications

Yueh Chin Lin^*, Jing Neng Yao, Hisang Hua Hsu, Ying Chieh Wong, Chi Yi Huang, Heng-Tung Hsu, Hiroshi Iwai, Edward Yi Chang

^*此作品的通信作者

研究成果: Paper › 同行評審

3 引文斯高帕斯（Scopus）

摘要

InAs HEMTs with a mesa etch structure that connects the Schottky gate through mesa sidewall with InAlAs layers were fabricated. The gate metal connection to the InAlAs layers increases the positive potential of the channel region through the gate bias, resulting in a steep SS due to a positive potential feedback. The mesa etch InAs HEMT shows an excellent performance with an extremely low minimum SS value of 46 mV/decade with the high G _{m, max} /SS of 33 and a high Ion/Ioff ratio of 6.6×10⁴ at V_ds = 1V.

原文	American English
頁面	1-3
頁數	3
DOIs	https://doi.org/10.1109/CSTIC.2018.8369315
出版狀態	Published - 29 5月 2018
事件	2018 China Semiconductor Technology International Conference, CSTIC 2018 - Shanghai, China 持續時間: 11 3月 2018 → 12 3月 2018

Conference

Conference	2018 China Semiconductor Technology International Conference, CSTIC 2018
國家/地區	China
城市	Shanghai
期間	11/03/18 → 12/03/18

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10.1109/CSTIC.2018.8369315

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引用此

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title = "Study of the mesa etched tri-gate InAs HEMTs with extremely low SS for low-power logic applications",

abstract = "InAs HEMTs with a mesa etch structure that connects the Schottky gate through mesa sidewall with InAlAs layers were fabricated. The gate metal connection to the InAlAs layers increases the positive potential of the channel region through the gate bias, resulting in a steep SS due to a positive potential feedback. The mesa etch InAs HEMT shows an excellent performance with an extremely low minimum SS value of 46 mV/decade with the high G m, max /SS of 33 and a high Ion/Ioff ratio of 6.6×104 at Vds = 1V.",

keywords = "HEMTs, MODFETs, Logic gates, Indium compounds, Etching, Metals, Electric potential",

author = "Lin, {Yueh Chin} and Yao, {Jing Neng} and Hsu, {Hisang Hua} and Wong, {Ying Chieh} and Huang, {Chi Yi} and Heng-Tung Hsu and Hiroshi Iwai and Chang, {Edward Yi}",

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doi = "10.1109/CSTIC.2018.8369315",

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AU - Lin, Yueh Chin

AU - Yao, Jing Neng

AU - Hsu, Hisang Hua

AU - Wong, Ying Chieh

AU - Huang, Chi Yi

AU - Hsu, Heng-Tung

AU - Iwai, Hiroshi

AU - Chang, Edward Yi

PY - 2018/5/29

Y1 - 2018/5/29

N2 - InAs HEMTs with a mesa etch structure that connects the Schottky gate through mesa sidewall with InAlAs layers were fabricated. The gate metal connection to the InAlAs layers increases the positive potential of the channel region through the gate bias, resulting in a steep SS due to a positive potential feedback. The mesa etch InAs HEMT shows an excellent performance with an extremely low minimum SS value of 46 mV/decade with the high G m, max /SS of 33 and a high Ion/Ioff ratio of 6.6×104 at Vds = 1V.

AB - InAs HEMTs with a mesa etch structure that connects the Schottky gate through mesa sidewall with InAlAs layers were fabricated. The gate metal connection to the InAlAs layers increases the positive potential of the channel region through the gate bias, resulting in a steep SS due to a positive potential feedback. The mesa etch InAs HEMT shows an excellent performance with an extremely low minimum SS value of 46 mV/decade with the high G m, max /SS of 33 and a high Ion/Ioff ratio of 6.6×104 at Vds = 1V.

KW - HEMTs

KW - MODFETs

KW - Logic gates

KW - Indium compounds

KW - Etching

KW - Metals

KW - Electric potential

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T2 - 2018 China Semiconductor Technology International Conference, CSTIC 2018

Y2 - 11 March 2018 through 12 March 2018

ER -

Study of the mesa etched tri-gate InAs HEMTs with extremely low SS for low-power logic applications

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