TY - GEN
T1 - Study of Silicide Blocking for GGNMOS Performance and Turn-On Time in CMOS Process
AU - Chien, Er Wen
AU - Cheng, Hao En
AU - Lin, Chun Yu
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - In order to minimize the occurrence of ESD damage in integrated circuits, it is crucial to design protective circuits that can effectively prevent ESD destruction. One approach that has been widely adopted is the utilization of NMOS-based ESD protection circuits. Among the various NMOS-based ESD protection circuits, the gate-grounded NMOS (GGNMOS) has emerged as a prominent choice. This study focuses on utilizing the GGNMOS as a benchmark for ESD protection to enhance its performance.
AB - In order to minimize the occurrence of ESD damage in integrated circuits, it is crucial to design protective circuits that can effectively prevent ESD destruction. One approach that has been widely adopted is the utilization of NMOS-based ESD protection circuits. Among the various NMOS-based ESD protection circuits, the gate-grounded NMOS (GGNMOS) has emerged as a prominent choice. This study focuses on utilizing the GGNMOS as a benchmark for ESD protection to enhance its performance.
UR - http://www.scopus.com/inward/record.url?scp=85205795150&partnerID=8YFLogxK
U2 - 10.1109/ICCE-Taiwan62264.2024.10674485
DO - 10.1109/ICCE-Taiwan62264.2024.10674485
M3 - Conference contribution
AN - SCOPUS:85205795150
T3 - 11th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2024
SP - 787
EP - 788
BT - 11th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2024
Y2 - 9 July 2024 through 11 July 2024
ER -