TY - JOUR
T1 - Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
AU - Yeh, Chih Ting
AU - Ker, Ming-Dou
PY - 2012/6/1
Y1 - 2012/6/1
N2 - To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (R ON C ESD, I CP/C ESD, V HBM/C ESD, and I CP/A Layout) of ESD protection diodes with new proposed layout styles can be successfully improved.
AB - To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (R ON C ESD, I CP/C ESD, V HBM/C ESD, and I CP/A Layout) of ESD protection diodes with new proposed layout styles can be successfully improved.
UR - http://www.scopus.com/inward/record.url?scp=84861531606&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2011.12.003
DO - 10.1016/j.microrel.2011.12.003
M3 - Article
AN - SCOPUS:84861531606
SN - 0026-2714
VL - 52
SP - 1020
EP - 1030
JO - Microelectronics Reliability
JF - Microelectronics Reliability
IS - 6
ER -