Study and Verification on the Latch-Up Path between I/O pMOS and N-Type Decoupling Capacitors in 0.18-\mu m CMOS Technology

Chun Cheng Chen, Ming-Dou Ker*

*此作品的通信作者

研究成果: Article同行評審

10 引文 斯高帕斯(Scopus)

摘要

On-chip decoupling capacitors often formed by varactor or nMOS have been widely used to shunt the power-line noise in integrated-circuit products. Because the N+ cathode of these capacitors is connected to ground, an unexpected latch-up path between I/O pMOS and n-Type decoupling capacitors may be accidentally triggered on. In this paper, the non-Typical latch-up path between I/O pMOS and n-Type decoupling capacitors was investigated in 0.18-{\mu }\text{m} 1.8/3.3-V CMOS technology. The measurement results from the silicon chip with split test structures have verified that the n-Type decoupling capacitor near the I/O pMOS can cause a high risk of latch-up. Therefore, the layout rules between the decoupling capacitor and I/O devices should be carefully defined to prevent the occurrence of such an unexpected latch-up path.

原文English
文章編號8714051
頁(從 - 到)445-451
頁數7
期刊IEEE Transactions on Device and Materials Reliability
19
發行號2
DOIs
出版狀態Published - 6月 2019

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