摘要
On-chip decoupling capacitors often formed by varactor or nMOS have been widely used to shunt the power-line noise in integrated-circuit products. Because the N+ cathode of these capacitors is connected to ground, an unexpected latch-up path between I/O pMOS and n-Type decoupling capacitors may be accidentally triggered on. In this paper, the non-Typical latch-up path between I/O pMOS and n-Type decoupling capacitors was investigated in 0.18-{\mu }\text{m} 1.8/3.3-V CMOS technology. The measurement results from the silicon chip with split test structures have verified that the n-Type decoupling capacitor near the I/O pMOS can cause a high risk of latch-up. Therefore, the layout rules between the decoupling capacitor and I/O devices should be carefully defined to prevent the occurrence of such an unexpected latch-up path.
原文 | English |
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文章編號 | 8714051 |
頁(從 - 到) | 445-451 |
頁數 | 7 |
期刊 | IEEE Transactions on Device and Materials Reliability |
卷 | 19 |
發行號 | 2 |
DOIs | |
出版狀態 | Published - 6月 2019 |