ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits.
|出版狀態||Published - 1 1月 1997|
|事件||Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn|
持續時間: 28 1月 1997 → 31 1月 1997
|Conference||Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC|
|期間||28/01/97 → 31/01/97|