Structural and electrical properties of high-k HoTiO3 gate dielectrics

Tung Ming Pan*, Li Chen Yen, Chia Wei Hu, Tien-Sheng Chao

*此作品的通信作者

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

We developed a high-k HoTiO3 gate dielectric deposited on Si (100) through reactive cosputtering. They found that the HoTiO3 dielectrics annealed at 800°C exhibited excellent electrical properties such as high capacitance value, small density of interface state, almost no hysteresis voltage, and low leakage current. This phenomenon is attributed to the decrease in intrinsic defect due to the formation of well-crystallized HoTiO3 structure and composition.

原文English
主出版物標題Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6
主出版物子標題New Materials, Processes, and Equipment
頁面241-245
頁數5
版本1
DOIs
出版狀態Published - 30 12月 2010
事件Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting - Vancouver, BC, 加拿大
持續時間: 26 4月 201027 4月 2010

出版系列

名字ECS Transactions
號碼1
28
ISSN(列印)1938-5862
ISSN(電子)1938-6737

Conference

ConferenceAdvanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting
國家/地區加拿大
城市Vancouver, BC
期間26/04/1027/04/10

指紋

深入研究「Structural and electrical properties of high-k HoTiO3 gate dielectrics」主題。共同形成了獨特的指紋。

引用此