Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

Chien Hao Chen*, T. L. Lee, Tuo-Hung Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, M. S. Liang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    131 引文 斯高帕斯(Scopus)

    摘要

    An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a Stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process, it was found to gain additional ∼10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.

    原文English
    主出版物標題2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS
    發行者IEEE
    頁面56-57
    頁數2
    ISBN(列印)0-7803-8289-7
    DOIs
    出版狀態Published - 1 10月 2004
    事件2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
    持續時間: 15 6月 200417 6月 2004

    出版系列

    名字Digest of Technical Papers - Symposium on VLSI Technology
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISSN(列印)0743-1562

    Conference

    Conference2004 Symposium on VLSI Technology - Digest of Technical Papers
    國家/地區United States
    城市Honolulu, HI
    期間15/06/0417/06/04

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