@inproceedings{7384bd4f5b4b4574ac95d79926d297d8,
title = "Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application",
abstract = "An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a Stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process, it was found to gain additional ∼10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.",
keywords = "Nitride, SMT, Stained-Si, Stress",
author = "Chen, {Chien Hao} and Lee, {T. L.} and Tuo-Hung Hou and Chen, {C. L.} and Chen, {C. C.} and Hsu, {J. W.} and Cheng, {K. L.} and Chiu, {Y. H.} and Tao, {H. J.} and Y. Jin and Diaz, {C. H.} and Chen, {S. C.} and Liang, {M. S.}",
year = "2004",
month = oct,
day = "1",
doi = "10.1109/VLSIT.2004.1345390",
language = "English",
isbn = "0-7803-8289-7",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "IEEE",
pages = "56--57",
booktitle = "2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS",
note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",
}