Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling

Fu Liang Yang; Hou Yu Chen; Chien Chao Huang; Chun Hu Ge; Ke Wei Su; Cheng Chuan Huang; Chang Yun Chang; Da Wen Lin; Chung Cheng Wu; Jaw Kang Ho; Wen Chin Lee; Yee Chia Yeo; Carlos H. Diaz; Mong Song Liang; Jack Y.C. Sun; Chen-Ming Hu

doi:10.1109/VLSIT.2003.1221123

Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling

Fu Liang Yang^*, Hou Yu Chen, Chien Chao Huang, Chun Hu Ge, Ke Wei Su, Cheng Chuan Huang, Chang Yun Chang, Da Wen Lin, Chung Cheng Wu, Jaw Kang Ho, Wen Chin Lee, Yee Chia Yeo, Carlos H. Diaz, Mong Song Liang, Jack Y.C. Sun, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

10 引文斯高帕斯（Scopus）

摘要

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

原文	English
頁（從 - 到）	137-138
頁數	2
期刊	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2003.1221123
出版狀態	Published - 2003
事件	2003 Symposium on VLSI Technology - Kyoto, 日本持續時間: 10 6月 2003 → 12 6月 2003

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10.1109/VLSIT.2003.1221123

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Yang, F. L., Chen, H. Y., Huang, C. C., Ge, C. H., Su, K. W., Huang, C. C., Chang, C. Y., Lin, D. W., Wu, C. C., Ho, J. K., Lee, W. C., Yeo, Y. C., Diaz, C. H., Liang, M. S., Sun, J. Y. C., & Hu, C.-M. (2003). Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling. Digest of Technical Papers - Symposium on VLSI Technology, 137-138. https://doi.org/10.1109/VLSIT.2003.1221123

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title = "Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling",

abstract = "A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.",

author = "Yang, {Fu Liang} and Chen, {Hou Yu} and Huang, {Chien Chao} and Ge, {Chun Hu} and Su, {Ke Wei} and Huang, {Cheng Chuan} and Chang, {Chang Yun} and Lin, {Da Wen} and Wu, {Chung Cheng} and Ho, {Jaw Kang} and Lee, {Wen Chin} and Yeo, {Yee Chia} and Diaz, {Carlos H.} and Liang, {Mong Song} and Sun, {Jack Y.C.} and Chen-Ming Hu",

year = "2003",

doi = "10.1109/VLSIT.2003.1221123",

language = "English",

pages = "137--138",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2003 Symposium on VLSI Technology ; Conference date: 10-06-2003 Through 12-06-2003",

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TY - JOUR

T1 - Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling

AU - Yang, Fu Liang

AU - Chen, Hou Yu

AU - Huang, Chien Chao

AU - Ge, Chun Hu

AU - Su, Ke Wei

AU - Huang, Cheng Chuan

AU - Chang, Chang Yun

AU - Lin, Da Wen

AU - Wu, Chung Cheng

AU - Ho, Jaw Kang

AU - Lee, Wen Chin

AU - Yeo, Yee Chia

AU - Diaz, Carlos H.

AU - Liang, Mong Song

AU - Sun, Jack Y.C.

AU - Hu, Chen-Ming

PY - 2003

Y1 - 2003

N2 - A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

AB - A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

UR - http://www.scopus.com/inward/record.url?scp=0141426799&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2003.1221123

DO - 10.1109/VLSIT.2003.1221123

M3 - Conference article

AN - SCOPUS:0141426799

SN - 0743-1562

SP - 137

EP - 138

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2003 Symposium on VLSI Technology

Y2 - 10 June 2003 through 12 June 2003

ER -

Strained FIP-SOI (FinFET/FD/PD-SOI) for Sub-65 nm CMOS Scaling

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