Stochastic STT-MRAM Spiking Neuron Circuit

Fu Xiang Liang; Paritosh Sahu; Ming Hung Wu; Jeng Hua Wei; Shyh Shyuan Sheu; Tuo Hung Hou

doi:10.1109/VLSI-TSA48913.2020.9203701

Stochastic STT-MRAM Spiking Neuron Circuit

Fu Xiang Liang, Paritosh Sahu, Ming Hung Wu, Jeng Hua Wei, Shyh Shyuan Sheu, Tuo Hung Hou^*

^*此作品的通信作者

電子研究所

研究成果: Conference contribution › 同行評審

4 引文斯高帕斯（Scopus）

摘要

We propose a compact STT-MRAM spiking neuron circuit that is a critical component of future hardware neural networks for accelerating deep learning. A SPICE compact model was established for the stochastic back-hopping oscillation of STT-MRAM, and the complete functionality of the spiking neuron circuit was demonstrated. Comparing to other emerging neuron circuits based on non-volatile memory (NVM) and the conventional capacitor-based integrate-and fire CMOS neuron circuit, this STT-MRAM spiking neuron circuit achieves the smallest area of 26 m by using the 65nm technology. For event-based spiking neural networks, this neuron circuit provides a competitive spiking rate of 100 kHz. For accurate analog-to-digital conversions in deep neural networks, this neuron circuit achieves a 4- bit resolution with minimal quantization error.

原文	English
主出版物標題	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	151-152
頁數	2
ISBN（電子）	9781728142326
DOIs	https://doi.org/10.1109/VLSI-TSA48913.2020.9203701
出版狀態	Published - 8月 2020
事件	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan 持續時間: 10 8月 2020 → 13 8月 2020

出版系列

名字	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
國家/地區	Taiwan
城市	Hsinchu
期間	10/08/20 → 13/08/20

存取文件

10.1109/VLSI-TSA48913.2020.9203701

其它文件與鏈接

Link to publication in Scopus

引用此

Liang, F. X., Sahu, P., Wu, M. H., Wei, J. H., Sheu, S. S., & Hou, T. H. (2020). Stochastic STT-MRAM Spiking Neuron Circuit. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 (頁 151-152). [9203701] (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA48913.2020.9203701

@inproceedings{c26330f0e6a544cb821c17c7ddf72026,

title = "Stochastic STT-MRAM Spiking Neuron Circuit",

abstract = "We propose a compact STT-MRAM spiking neuron circuit that is a critical component of future hardware neural networks for accelerating deep learning. A SPICE compact model was established for the stochastic back-hopping oscillation of STT-MRAM, and the complete functionality of the spiking neuron circuit was demonstrated. Comparing to other emerging neuron circuits based on non-volatile memory (NVM) and the conventional capacitor-based integrate-and fire CMOS neuron circuit, this STT-MRAM spiking neuron circuit achieves the smallest area of 26 m by using the 65nm technology. For event-based spiking neural networks, this neuron circuit provides a competitive spiking rate of 100 kHz. For accurate analog-to-digital conversions in deep neural networks, this neuron circuit achieves a 4- bit resolution with minimal quantization error.",

author = "Liang, {Fu Xiang} and Paritosh Sahu and Wu, {Ming Hung} and Wei, {Jeng Hua} and Sheu, {Shyh Shyuan} and Hou, {Tuo Hung}",

year = "2020",

month = aug,

doi = "10.1109/VLSI-TSA48913.2020.9203701",

language = "English",

series = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "151--152",

booktitle = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

address = "United States",

}

Liang, FX, Sahu, P, Wu, MH, Wei, JH, Sheu, SS & Hou, TH 2020, Stochastic STT-MRAM Spiking Neuron Circuit. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020., 9203701, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Institute of Electrical and Electronics Engineers Inc., 頁 151-152, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Hsinchu, Taiwan, 10/08/20. https://doi.org/10.1109/VLSI-TSA48913.2020.9203701

Stochastic STT-MRAM Spiking Neuron Circuit. / Liang, Fu Xiang; Sahu, Paritosh; Wu, Ming Hung 等.

2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 151-152 9203701 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Stochastic STT-MRAM Spiking Neuron Circuit

AU - Liang, Fu Xiang

AU - Sahu, Paritosh

AU - Wu, Ming Hung

AU - Wei, Jeng Hua

AU - Sheu, Shyh Shyuan

AU - Hou, Tuo Hung

PY - 2020/8

Y1 - 2020/8

N2 - We propose a compact STT-MRAM spiking neuron circuit that is a critical component of future hardware neural networks for accelerating deep learning. A SPICE compact model was established for the stochastic back-hopping oscillation of STT-MRAM, and the complete functionality of the spiking neuron circuit was demonstrated. Comparing to other emerging neuron circuits based on non-volatile memory (NVM) and the conventional capacitor-based integrate-and fire CMOS neuron circuit, this STT-MRAM spiking neuron circuit achieves the smallest area of 26 m by using the 65nm technology. For event-based spiking neural networks, this neuron circuit provides a competitive spiking rate of 100 kHz. For accurate analog-to-digital conversions in deep neural networks, this neuron circuit achieves a 4- bit resolution with minimal quantization error.

AB - We propose a compact STT-MRAM spiking neuron circuit that is a critical component of future hardware neural networks for accelerating deep learning. A SPICE compact model was established for the stochastic back-hopping oscillation of STT-MRAM, and the complete functionality of the spiking neuron circuit was demonstrated. Comparing to other emerging neuron circuits based on non-volatile memory (NVM) and the conventional capacitor-based integrate-and fire CMOS neuron circuit, this STT-MRAM spiking neuron circuit achieves the smallest area of 26 m by using the 65nm technology. For event-based spiking neural networks, this neuron circuit provides a competitive spiking rate of 100 kHz. For accurate analog-to-digital conversions in deep neural networks, this neuron circuit achieves a 4- bit resolution with minimal quantization error.

UR - http://www.scopus.com/inward/record.url?scp=85093676804&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA48913.2020.9203701

DO - 10.1109/VLSI-TSA48913.2020.9203701

M3 - Conference contribution

AN - SCOPUS:85093676804

T3 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

SP - 151

EP - 152

BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 10 August 2020 through 13 August 2020

ER -

Liang FX, Sahu P, Wu MH, Wei JH, Sheu SS, Hou TH. Stochastic STT-MRAM Spiking Neuron Circuit. 於 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 151-152. 9203701. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). doi: 10.1109/VLSI-TSA48913.2020.9203701

Stochastic STT-MRAM Spiking Neuron Circuit

摘要

出版系列

Conference

存取文件

其它文件與鏈接

指紋

引用此