摘要
Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.
原文 | English |
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頁面 | 2621-2624 |
頁數 | 4 |
DOIs | |
出版狀態 | Published - 28 9月 2012 |
事件 | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of 持續時間: 20 5月 2012 → 23 5月 2012 |
Conference
Conference | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 |
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國家/地區 | Korea, Republic of |
城市 | Seoul |
期間 | 20/05/12 → 23/05/12 |