Steep-slope hysteresis-free negative capacitance MoS2 transistors

Mengwei Si, Chun Jung Su, Chunsheng Jiang, Nathan J. Conrad, Hong Zhou, Kerry D. Maize, Gang Qiu, Chien Ting Wu, Ali Shakouri, Muhammad A. Alam, Peide D. Ye*

*此作品的通信作者

研究成果: Article同行評審

414 引文 斯高帕斯(Scopus)

摘要

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption 1,2 . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier 3 . Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel 4-12 . Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

原文English
頁(從 - 到)24-28
頁數5
期刊Nature nanotechnology
13
發行號1
DOIs
出版狀態Published - 1 1月 2018

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