Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel

Ang Sheng Chou; Ching Hao Hsu; Yu Tung Lin; Goutham Arutchelvan; Edward Chen; Terry Y.T. Hung; Chen Feng Hsu; Sui An Chou; Tsung En Lee; Oreste Madia; Gerben Doornbos; Yuan Chun Su; Amin Azizi; D. Mahaveer Sathaiya; Jin Cai; Jer Fu Wang; Yun Yan Chung; Wen Chia Wu; Katie Neilson; Wei Sheng Yun; Yu Wei Hsu; Ming Chun Hsu; Fa Rong Hou; Yun Yang Shen; Chao Hsin Chien; Chung Cheng Wu; Jeff Wu; H. S.Philip Wong; Wen Hao Chang; Mark Van Dal; Chao Ching Cheng; Chih I. Wu; Iuliana P. Radu

doi:10.1109/IEDM45741.2023.10413779

Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel

Ang Sheng Chou^*, Ching Hao Hsu, Yu Tung Lin, Goutham Arutchelvan, Edward Chen, Terry Y.T. Hung, Chen Feng Hsu, Sui An Chou, Tsung En Lee, Oreste Madia, Gerben Doornbos, Yuan Chun Su, Amin Azizi, D. Mahaveer Sathaiya, Jin Cai, Jer Fu Wang, Yun Yan Chung, Wen Chia Wu, Katie Neilson, Wei Sheng YunYu Wei Hsu, Ming Chun Hsu, Fa Rong Hou, Yun Yang Shen, Chao Hsin Chien, Chung Cheng Wu, Jeff Wu, H. S.Philip Wong, Wen Hao Chang, Mark Van Dal, Chao Ching Cheng, Chih I. Wu, Iuliana P. Radu

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm²/V•s. We demonstrate scaling of nMOS contact length (L_C) to 12 nm and top gate length (L_G) to 10 nm. Devices maintain high current density at short L_C as well as in top-gate only operation.

原文	English
主出版物標題	2023 International Electron Devices Meeting, IEDM 2023
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9798350327670
DOIs	https://doi.org/10.1109/IEDM45741.2023.10413779
出版狀態	Published - 2023
事件	2023 International Electron Devices Meeting, IEDM 2023 - San Francisco, United States 持續時間: 9 12月 2023 → 13 12月 2023

出版系列

名字	Technical Digest - International Electron Devices Meeting, IEDM
ISSN（列印）	0163-1918

Conference

Conference	2023 International Electron Devices Meeting, IEDM 2023
國家/地區	United States
城市	San Francisco
期間	9/12/23 → 13/12/23

存取文件

10.1109/IEDM45741.2023.10413779

其它文件與鏈接

Link to publication in Scopus

引用此

Chou, A. S., Hsu, C. H., Lin, Y. T., Arutchelvan, G., Chen, E., Hung, T. Y. T., Hsu, C. F., Chou, S. A., Lee, T. E., Madia, O., Doornbos, G., Su, Y. C., Azizi, A., Sathaiya, D. M., Cai, J., Wang, J. F., Chung, Y. Y., Wu, W. C., Neilson, K., ... Radu, I. P. (2023). Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel. 於 2023 International Electron Devices Meeting, IEDM 2023 (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM45741.2023.10413779

@inproceedings{50c781082b6e4fb09e7f112c3b2a22bd,

title = "Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel",

abstract = "Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm2/V•s. We demonstrate scaling of nMOS contact length (LC) to 12 nm and top gate length (LG) to 10 nm. Devices maintain high current density at short LC as well as in top-gate only operation.",

author = "Chou, {Ang Sheng} and Hsu, {Ching Hao} and Lin, {Yu Tung} and Goutham Arutchelvan and Edward Chen and Hung, {Terry Y.T.} and Hsu, {Chen Feng} and Chou, {Sui An} and Lee, {Tsung En} and Oreste Madia and Gerben Doornbos and Su, {Yuan Chun} and Amin Azizi and Sathaiya, {D. Mahaveer} and Jin Cai and Wang, {Jer Fu} and Chung, {Yun Yan} and Wu, {Wen Chia} and Katie Neilson and Yun, {Wei Sheng} and Hsu, {Yu Wei} and Hsu, {Ming Chun} and Hou, {Fa Rong} and Shen, {Yun Yang} and Chien, {Chao Hsin} and Wu, {Chung Cheng} and Jeff Wu and Wong, {H. S.Philip} and Chang, {Wen Hao} and {Van Dal}, Mark and Cheng, {Chao Ching} and Wu, {Chih I.} and Radu, {Iuliana P.}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International Electron Devices Meeting, IEDM 2023 ; Conference date: 09-12-2023 Through 13-12-2023",

year = "2023",

doi = "10.1109/IEDM45741.2023.10413779",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 International Electron Devices Meeting, IEDM 2023",

address = "United States",

}

Chou, AS, Hsu, CH, Lin, YT, Arutchelvan, G, Chen, E, Hung, TYT, Hsu, CF, Chou, SA, Lee, TE, Madia, O, Doornbos, G, Su, YC, Azizi, A, Sathaiya, DM, Cai, J, Wang, JF, Chung, YY, Wu, WC, Neilson, K, Yun, WS, Hsu, YW, Hsu, MC, Hou, FR, Shen, YY, Chien, CH, Wu, CC, Wu, J, Wong, HSP, Chang, WH, Van Dal, M, Cheng, CC, Wu, CI & Radu, IP 2023, Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel. 於 2023 International Electron Devices Meeting, IEDM 2023. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., 2023 International Electron Devices Meeting, IEDM 2023, San Francisco, United States, 9/12/23. https://doi.org/10.1109/IEDM45741.2023.10413779

Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel. / Chou, Ang Sheng; Hsu, Ching Hao; Lin, Yu Tung 等.
2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel

AU - Chou, Ang Sheng

AU - Hsu, Ching Hao

AU - Lin, Yu Tung

AU - Arutchelvan, Goutham

AU - Chen, Edward

AU - Hung, Terry Y.T.

AU - Hsu, Chen Feng

AU - Chou, Sui An

AU - Lee, Tsung En

AU - Madia, Oreste

AU - Doornbos, Gerben

AU - Su, Yuan Chun

AU - Azizi, Amin

AU - Sathaiya, D. Mahaveer

AU - Cai, Jin

AU - Wang, Jer Fu

AU - Chung, Yun Yan

AU - Wu, Wen Chia

AU - Neilson, Katie

AU - Yun, Wei Sheng

AU - Hsu, Yu Wei

AU - Hsu, Ming Chun

AU - Hou, Fa Rong

AU - Shen, Yun Yang

AU - Chien, Chao Hsin

AU - Wu, Chung Cheng

AU - Wu, Jeff

AU - Wong, H. S.Philip

AU - Chang, Wen Hao

AU - Van Dal, Mark

AU - Cheng, Chao Ching

AU - Wu, Chih I.

AU - Radu, Iuliana P.

PY - 2023

Y1 - 2023

N2 - Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm2/V•s. We demonstrate scaling of nMOS contact length (LC) to 12 nm and top gate length (LG) to 10 nm. Devices maintain high current density at short LC as well as in top-gate only operation.

AB - Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm2/V•s. We demonstrate scaling of nMOS contact length (LC) to 12 nm and top gate length (LG) to 10 nm. Devices maintain high current density at short LC as well as in top-gate only operation.

UR - http://www.scopus.com/inward/record.url?scp=85185573058&partnerID=8YFLogxK

U2 - 10.1109/IEDM45741.2023.10413779

DO - 10.1109/IEDM45741.2023.10413779

M3 - Conference contribution

AN - SCOPUS:85185573058

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2023 International Electron Devices Meeting, IEDM 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 International Electron Devices Meeting, IEDM 2023

Y2 - 9 December 2023 through 13 December 2023

ER -

Chou AS, Hsu CH, Lin YT, Arutchelvan G, Chen E, Hung TYT 等. Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel. 於 2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM45741.2023.10413779

Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel

摘要

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Conference

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