@inproceedings{b5e9851eb7a24deea89f2694348a2ddd,
title = "Statistical techniques for predicting system-level failure using stress-test data",
abstract = "In this paper we describe a novel scheme for collecting and analyzing a chip's failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip's 'analog' failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.",
author = "Chen, {Harry H.} and Kuo, {Shih Hua} and Jonathan Tung and Chia-Tso Chao",
year = "2015",
month = jun,
day = "1",
doi = "10.1109/VTS.2015.7116260",
language = "English",
series = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE Computer Society",
booktitle = "Proceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015",
address = "美國",
note = "2015 33rd IEEE VLSI Test Symposium, VTS 2015 ; Conference date: 27-04-2015 Through 29-04-2015",
}