Statistical techniques for predicting system-level failure using stress-test data

Harry H. Chen, Shih Hua Kuo, Jonathan Tung, Chia-Tso Chao

研究成果: Conference contribution同行評審

9 引文 斯高帕斯(Scopus)

摘要

In this paper we describe a novel scheme for collecting and analyzing a chip's failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip's 'analog' failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.

原文English
主出版物標題Proceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015
發行者IEEE Computer Society
ISBN(電子)9781479975976
DOIs
出版狀態Published - 1 6月 2015
事件2015 33rd IEEE VLSI Test Symposium, VTS 2015 - Napa, United States
持續時間: 27 4月 201529 4月 2015

出版系列

名字Proceedings of the IEEE VLSI Test Symposium
2015-January

Conference

Conference2015 33rd IEEE VLSI Test Symposium, VTS 2015
國家/地區United States
城市Napa
期間27/04/1529/04/15

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