Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators

Szu Pang Mu, Chia-Tso Chao, Shi Hao Chen, Yi Ming Wang

研究成果: Article同行評審

19 引文 斯高帕斯(Scopus)

摘要

This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip's maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel built-in self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip.

原文English
文章編號7294704
頁(從 - 到)1675-1687
頁數13
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
24
發行號5
DOIs
出版狀態Published - 1 5月 2016

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