Statistical fluctuations of dopant impurities in ion-implanted bipolar transistor structures and the minimum device dimensions for vlsi system reliability

P. R. Prucnal*, Wei Hwang, H. C. Card

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3 引文 斯高帕斯(Scopus)

摘要

The minimum dimensions of bipolar transistors with ion implanted impurity profiles for predictable device and system behavior is calculated on the basis of limitations arising from the random positions of the implanted impurities. Doubly-stochastic effects arising from uncertainty in exact implantation parameters are included, and are shown to be of first order importance in the specification of minimum size for a given chip yield. For example, a ± 10% uncertainty in the standard deviation of one of the implants has been found to increase the minimum dimension by approximately a factor of 4. For a chip yield of 99% against this limitation, the minimum emitter size is of the order of 1 ≲ L ≲ 5 μm when a straight-forward scaling theory is applied to dimensions and impurity concentrations from present device designs and a parity check on a bit word is applied.

原文English
頁(從 - 到)633-646
頁數14
期刊Microelectronics Reliability
20
發行號5
DOIs
出版狀態Published - 1 1月 1980

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