State retention for power gated design with non-uniform multi-bit retention latches

Guo Gin Fan, Po-Hung Lin

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

Retention registers/latches are commonly applied to power-gated circuits for state retention during the sleep mode. Recent studies have shown that applying uniform multi-bit retention registers (MBRRs) can reduce the storage size, and hence save more chip area and leakage power compared with single-bit retention registers. In this paper, a new problem formulation of power-gated circuit optimization with nonuniform MBRRs is studied for achieving even more storage saving and higher storage utilization. An ILP-based approach is proposed to effectively explore different combinations of nonuniform MBRR replacement. Experiment results show that the proposed approach can reduce 36% storage size, compared with the state-of-the-art uniform MBRR replacement, while achieving 100% storage utilization.

原文English
主出版物標題2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面607-614
頁數8
ISBN(電子)9781538630938
DOIs
出版狀態Published - 13 十二月 2017
事件36th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017 - Irvine, United States
持續時間: 13 十一月 201716 十一月 2017

出版系列

名字IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
2017-November
ISSN(列印)1092-3152

Conference

Conference36th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017
國家/地區United States
城市Irvine
期間13/11/1716/11/17

指紋

深入研究「State retention for power gated design with non-uniform multi-bit retention latches」主題。共同形成了獨特的指紋。

引用此