TY - JOUR
T1 - Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses
AU - Hsueh, Cheng-Yun
AU - Ker, Ming-Dou
PY - 2021/4
Y1 - 2021/4
N2 - Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-mu m CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail.
AB - Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-mu m CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail.
KW - Charged-device model (CDM)
KW - cross-domainESD protection
KW - electrostatic discharge (ESD) protection
KW - multiple power domains
KW - stacking metal-oxide-semiconductor (MOS) structure
U2 - 10.1109/TED.2021.3061325
DO - 10.1109/TED.2021.3061325
M3 - Article
SN - 0018-9383
VL - 68
SP - 1461
EP - 1470
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 4
ER -