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Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs with RTA-Improved Crystallinity
Chiuan Huei Shen, Po Yi Kuo, Chun Chih Chung, Sen Yang Lee,
Tien-Sheng Chao
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此作品的通信作者
電子物理學系
研究成果
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5
引文 斯高帕斯(Scopus)
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Keyphrases
Poly-Si
100%
Double Layer
100%
Sidewall
100%
Field-effect Transistors
100%
Rapid Thermal Annealing
100%
Tri-gate
100%
Damascene
100%
Improved Crystallinity
100%
Crystallinity
25%
Electrical Characteristics
25%
Fabrication Methods
25%
Current Ratio
25%
Drain Induced Barrier Lowering
25%
Simple Fabrication
25%
Polysilicon
12%
Order of Magnitude
12%
P-type
12%
3D IC
12%
Subthreshold Swing
12%
Circuit Application
12%
High Field-effect Mobility
12%
High Current
12%
Large Grain Size
12%
Steep Subthreshold Swing
12%
Monolithic 3-D (M3-D)
12%
Engineering
Crystallinity
100%
Field-Effect Transistor
100%
Side Wall
100%
Rapid Thermal Annealing
100%
Double Layer
100%
Polysilicon
100%
Current Ratio
25%
Fabrication Method
25%
Three Dimensional Integrated Circuits
12%
Promising Candidate
12%
Material Science
Field Effect Transistor
100%
Electrical Property
50%
Silicon
25%
Electronic Circuit
25%
Grain Size
25%