Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs with RTA-Improved Crystallinity

Chiuan Huei Shen, Po Yi Kuo, Chun Chih Chung, Sen Yang Lee, Tien-Sheng Chao*

*此作品的通信作者

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this letter, stacked sidewall-damascene double-layer poly-silicon trigate field effect transistors (FETs) with and without rapid thermal annealing (RTA) are successfully demonstrated using a simple fabrication method. Devices with RTA exhibit superior electrical characteristics to those without RTA owing to better crystallinity. The better crystallinity of the device with RTA results from a larger grain size and fewer defects, leading to higher field-effect mobility compared with devices without RTA. p-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA show excellent electrical characteristics, including an extremely low drain-induced barrier lowering (DIBL) of 7 mV/V, a steep subthreshold swing of 136 mV/decade, and high current ratio of. The fabricated n-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA showed a low DIBL, subthreshold swing and an current ratio larger than seven orders of magnitude. Their simple fabrication method makes them a promising candidate for future monolithic 3D integrated-circuit applications.

原文English
頁(從 - 到)512-515
頁數4
期刊IEEE Electron Device Letters
39
發行號4
DOIs
出版狀態Published - 1 4月 2018

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